EP1S40F1020I6N Altera, EP1S40F1020I6N Datasheet - Page 138
EP1S40F1020I6N
Manufacturer Part Number
EP1S40F1020I6N
Description
IC STRATIX FPGA 40K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S40F1020I6N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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I/O Structure
2–124
Stratix Device Handbook, Volume 1
f
For more information on I/O standards supported by Stratix devices, see
the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the
Stratix Device Handbook, Volume 2.
Stratix devices contain eight I/O banks in addition to the four enhanced
PLL external clock out banks, as shown in
banks on the right and left of the device contain circuitry to support high-
speed differential I/O for LVDS, LVPECL, 3.3-V PCML, and
HyperTransport inputs and outputs. These banks support all I/O
standards listed in
SSTL-18 Class II, and HSTL Class II outputs. The top and bottom I/O
banks support all single-ended I/O standards. Additionally, Stratix
devices support four enhanced PLL external clock output banks,
allowing clock output capabilities such as differential support for SSTL
and HSTL.
Table 2–32
Table 2–31
shows I/O standard support for each I/O bank.
except PCI I/O pins or PCI-X 1.0, GTL,
Figure
2–70. The four I/O
Altera Corporation
July 2005
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