EP1S40F1020I6 Altera, EP1S40F1020I6 Datasheet - Page 138
EP1S40F1020I6
Manufacturer Part Number
EP1S40F1020I6
Description
IC STRATIX FPGA 40K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S40F1020I6
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
41250
# I/os (max)
773
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1862
EP1S40F1020I6
EP1S40F1020I6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S40F1020I6
Manufacturer:
NEC
Quantity:
9 760
Company:
Part Number:
EP1S40F1020I6
Manufacturer:
ALTERA40
Quantity:
140
Part Number:
EP1S40F1020I6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
I/O Structure
2–124
Stratix Device Handbook, Volume 1
f
For more information on I/O standards supported by Stratix devices, see
the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the
Stratix Device Handbook, Volume 2.
Stratix devices contain eight I/O banks in addition to the four enhanced
PLL external clock out banks, as shown in
banks on the right and left of the device contain circuitry to support high-
speed differential I/O for LVDS, LVPECL, 3.3-V PCML, and
HyperTransport inputs and outputs. These banks support all I/O
standards listed in
SSTL-18 Class II, and HSTL Class II outputs. The top and bottom I/O
banks support all single-ended I/O standards. Additionally, Stratix
devices support four enhanced PLL external clock output banks,
allowing clock output capabilities such as differential support for SSTL
and HSTL.
Table 2–32
Table 2–31
shows I/O standard support for each I/O bank.
except PCI I/O pins or PCI-X 1.0, GTL,
Figure
2–70. The four I/O
Altera Corporation
July 2005