EP2S90F1020C5 Altera, EP2S90F1020C5 Datasheet - Page 57
EP2S90F1020C5
Manufacturer Part Number
EP2S90F1020C5
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S90F1020C5
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1465
EP2S90F1020C5
EP2S90F1020C5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S90F1020C5N
Manufacturer:
ALTERA
Quantity:
233
Company:
Part Number:
EP2S90F1020C5N
Manufacturer:
ALTERA
Quantity:
530
Altera Corporation
May 2007
global clock networks can also be driven by internal logic for internally
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout.
pins driving global clock networks.
Figure 2–31. Global Clocking
Regional Clock Network
There are eight regional clock networks RCLK[7..0] in each quadrant of
the Stratix II device that are driven by the dedicated CLK[15..0] input
pins, by PLL outputs, or by internal logic. The regional clock networks
provide the lowest clock delay and skew for logic contained in a single
quadrant. The CLK clock pins symmetrically drive the RCLK networks in
a particular quadrant, as shown in
CLK[3..0]
Global Clock [15..0]
CLK[7..4]
Figure 2–31
Figure
Stratix II Device Handbook, Volume 1
CLK[15..12]
Global Clock [15..0]
2–32.
shows the 16 dedicated CLK
Stratix II Architecture
CLK[11..8]
2–49