EP2SGX90EF1152C5ES Altera, EP2SGX90EF1152C5ES Datasheet - Page 13
EP2SGX90EF1152C5ES
Manufacturer Part Number
EP2SGX90EF1152C5ES
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX90EF1152C5ES
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1765
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Figure 2–3. Clock Distribution for the Transmitters
Note to
(1)
Altera Corporation
October 2007
Reference Clocks
(refclks,
Global Clock (1) ,
Inter-Transceiver
Lines)
The global clock line must be driven by an input pin.
Figure
2–3:
Central Block
Transmitter Channel [3..2]
Transmitter Channel [1..0]
Transmitter PLL Block
The transmitter PLLs in each transceiver block clock the PMA and PCS
circuitry in the transmit path. The Quartus II software automatically
powers down the transmitter PLLs that are not used in the design.
Figure 2–4
The transmitter phase/frequency detector references the clock from one
of the following sources:
■
■
■
■
Two reference clocks, REFCLK0 and REFCLK1, are available per
transceiver block. The inter-transceiver block bus allows multiple
transceivers to use the same reference clocks. Each transceiver block has
one outgoing reference clock which connects to one inter-transceiver
block line. The incoming reference clock can be selected from five
inter-transceiver block lines IQ[4..0] or from the global clock line that
is driven by an input pin.
Reference clocks
Reference clock from the adjacent transceiver block
Inter-transceiver block clock lines
Global clock line driven by input pin
is a block diagram of the transmitter PLL.
Note (1)
Transmitter Local
Clock Divider Block
Transmitter Local
Clock Divider Block
Central Clock
Gen Block
Divider Block
Gen Block
TX Clock
TX Clock
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
Transmitter High-Speed &
Transmitter High-Speed &
Low-Speed Clocks
Low-Speed Clocks
2–5
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