EP1SGX40DF1020C5 Altera, EP1SGX40DF1020C5 Datasheet - Page 165
EP1SGX40DF1020C5
Manufacturer Part Number
EP1SGX40DF1020C5
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
41250
# I/os (max)
624
Frequency (max)
5GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1SGX40DF1020C5
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1SGX40DF1020C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 4–60. Column I/O Block Connection to the Interconnect
Notes to
(1)
(2)
Altera Corporation
February 2005
The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0],
four clocks io_bclk[3..0], and four clear signals io_bclr[3..0].
The 42 data and control signals consist of 12 data out lines; six lines each for DDR applications
io_dataouta[5..0] and io_dataoutb[5..0], six output enables io_coe[5..0], six input clock enables
io_cce_in[5..0], six output clock enables io_cce_out[5..0], six clocks io_cclk[5..0], and six clear
signals io_cclr[5..0].
Figure
Local Interconnect
Signals from I/O
Interconnect (1)
from Logic Array (2)
R4, R8 & R24
Interconnects
4–60:
16 Control
I/O Block
Control Signals
42 Data &
Interconnect
LAB
LAB Local
16
Vertical I/O Block
Interconnects
C4, C8 & C16
42
LAB
Stratix GX Device Handbook, Volume 1
IO_datain[3:0]
LAB
Stratix GX Architecture
Vertical I/O
Block Contains
up to Six IOEs
io_clk[7..0]
I/O Interconnect
4–99
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