EP2S90F1508I4N Altera, EP2S90F1508I4N Datasheet - Page 87
EP2S90F1508I4N
Manufacturer Part Number
EP2S90F1508I4N
Description
IC STRATIX II FPGA 90K 1508-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S90F1508I4N
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
902
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1508-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
EP2S90F1508I4N
Manufacturer:
ALTERA
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586
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Figure 2–53. Input Timing Diagram in DDR Mode
Altera Corporation
May 2007
Input To
Logic Array
Data at
input pin
CLK
B0
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from ALMs on rising clock edges.
These output registers are multiplexed by the clock to drive the output
pin at a ×2 rate. One output register clocks the first bit out on the clock
high time, while the other output register clocks the second bit out on the
clock low time.
Figure 2–55
A0
B1
A0
B0
A1
shows the DDR output timing diagram.
Figure 2–54
B2
A1
B1
A2
B3
A2
B2
shows the IOE configured for DDR output.
A3
B4
A3
B3
Stratix II Device Handbook, Volume 1
Stratix II Architecture
2–79
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