EP2S90F1020C3 Altera, EP2S90F1020C3 Datasheet - Page 21
EP2S90F1020C3
Manufacturer Part Number
EP2S90F1020C3
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S90F1020C3
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1917
EP2S90F1020C3
EP2S90F1020C3
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Altera Corporation
May 2007
datae1 and dataf1 are utilized, the output drives to register1
and/or bypasses register1 and drives to the interconnect using the
bottom set of output drivers. The Quartus II Compiler automatically
selects the inputs to the LUT. Asynchronous load data for the register
comes from the datae or dataf input of the ALM. ALMs in normal
mode support register packing.
Figure 2–9. 6-Input Function in Normal Mode
Notes to
(1)
(2)
Extended LUT Mode
The extended LUT mode is used to implement a specific set of
seven-input functions. The set must be a 2-to-1 multiplexer fed by two
arbitrary five-input functions sharing four inputs.
template of supported seven-input functions utilizing extended LUT
mode. In this mode, if the seven-input function is unregistered, the
unused eighth input is available for register packing.
Functions that fit into the template shown in
in designs. These functions often appear in designs as “if-else” statements
in Verilog HDL or VHDL code.
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
(2)
If datae1 and dataf1 are used as inputs to the six-input function, then datae0
and dataf0 are available for register packing.
The dataf1 input is available for register packing only if the six-input function is
un-registered.
These inputs are available for register packing.
Figure
2–9:
6-Input
LUT
Stratix II Device Handbook, Volume 1
Notes
Figure 2–10
D
D
reg0
reg1
(1),
Figure 2–10
Q
Q
Stratix II Architecture
(2)
occur naturally
To general or
local routing
To general or
local routing
To general or
local routing
shows the
2–13
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