EP2S180F1020C5N Altera, EP2S180F1020C5N Datasheet - Page 27
EP2S180F1020C5N
Manufacturer Part Number
EP2S180F1020C5N
Description
IC STRATIX II FPGA 180K 1020FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S180F1020C5N
Number Of Logic Elements/cells
179400
Number Of Labs/clbs
8970
Total Ram Bits
9383040
Number Of I /o
742
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
For Use With
544-1701 - DSP PRO KIT W/SII EP2S180N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1885
EP2S180F1020C5N
EP2S180F1020C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S180F1020C5N
Manufacturer:
ALTERA
Quantity:
745
Part Number:
EP2S180F1020C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–14. Example of a 3-bit Add Utilizing Shared Arithmetic Mode
Altera Corporation
May 2007
3-Bit Add Example
implemented in adders.
implemented in LUTs.
+
2nd stage add is
1st stage add is
1 1 0 1
1 1 0
+
Binary Add
1 1 0
1 0 1
0 1 0
0 0 1
+
C2 C1 C0
R3 R2 R1 R0
Shared Arithmetic Chain
In addition to the dedicated carry chain routing, the shared arithmetic
chain available in shared arithmetic mode allows the ALM to implement
a three-input add. This significantly reduces the resources necessary to
implement large adder trees or correlator functions.
The shared arithmetic chains can begin in either the first or fifth ALM in
an LAB. The Quartus II Compiler creates shared arithmetic chains longer
than 16 (8 ALMs in arithmetic or shared arithmetic mode) by linking
LABs together automatically. For enhanced fitting, a long shared
+
+
Equivalents
Decimal
X2 X1 X0
S2 S1 S0
2 x 6
Y2 Y1 Y0
Z2 Z1 Z0
+
13
6
5
2
1
X0
Y0
Z0
X1
Y1
Z1
X2
Y2
Z2
ALM Implementation
ALM 1
ALM 2
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
Stratix II Device Handbook, Volume 1
S0
C0
S1
C1
S2
C2
shared_arith_in = '0'
'0'
carry_in = '0'
Stratix II Architecture
R0
R1
R2
R3
2–19
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