EP2S130F1020I5 Altera, EP2S130F1020I5 Datasheet - Page 59
EP2S130F1020I5
Manufacturer Part Number
EP2S130F1020I5
Description
IC STRATIX II FPGA 130K 1020FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S130F1020I5
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
742
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Company:
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EP2S130F1020I5
Manufacturer:
ALTERA
Quantity:
996
Part Number:
EP2S130F1020I5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Quantity:
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Figure 2–33. Dual-Regional Clocks
Figure 2–34. Hierarchical Clock Networks Per Quadrant
Altera Corporation
May 2007
PLLs
CLK[3..0]
Regional Clock Network [7..0]
Global Clock Network [15..0]
Clock Pins or PLL Clock Outputs
Can Drive Dual-Regional Network
CLK[7..4]
CLK[15..12]
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources
consisting of 16 global clock lines and eight regional clock lines.
Multiplexers are used with these clocks to form busses to drive LAB row
clocks, column IOE clocks, or row IOE clocks. Another multiplexer is
used at the LAB level to select three of the six row clocks to feed the ALM
registers in the LAB (see Figure 2–34).
CLK[11..8]
or Half-Quadrant
Clocks Available
to a Quadrant
Clock [23..0]
Clock Pins or PLL Clock
Outputs Can Drive
Dual-Regional Network
PLLs
CLK[3..0]
Stratix II Device Handbook, Volume 1
CLK[7..4]
CLK[15..12]
Stratix II Architecture
Column I/O Cell
IO_CLK[7..0]
Lab Row Clock [5..0]
Row I/O Cell
IO_CLK[7..0]
CLK[11..8]
2–51
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