EP1S80F1020C6 Altera, EP1S80F1020C6 Datasheet - Page 89
EP1S80F1020C6
Manufacturer Part Number
EP1S80F1020C6
Description
IC STRATIX FPGA 80K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S80F1020C6
Number Of Logic Elements/cells
79040
Number Of Labs/clbs
7904
Total Ram Bits
7427520
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1439
EP1S80F1020C6
EP1S80F1020C6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S80F1020C6
Manufacturer:
ALTERA
Quantity:
528
Part Number:
EP1S80F1020C6
Manufacturer:
ALTERA/阿尔特拉
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20 000
Part Number:
EP1S80F1020C6N
Manufacturer:
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Quantity:
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Altera Corporation
July 2005
Figure 2–42. Global Clocking
Note to
(1)
Regional Clock Network
There are four regional clock networks within each quadrant of the Stratix
device that are driven by the same dedicated CLK[15..0] input pins or
from PLL outputs. From a top view of the silicon, RCLK[0..3] are in the
top left quadrant, RCLK[8..11] are in the top-right quadrant,
RCLK[4..7] are in the bottom-left quadrant, and RCLK[12..15] are in
the bottom-right quadrant. The regional clock networks only pertain to
the quadrant they drive into. The regional clock networks provide the
lowest clock delay and skew for logic contained within a single quadrant.
RCLK cannot be driven by internal logic. The CLK clock pins
symmetrically drive the RCLK networks within a particular quadrant, as
shown in
from PLLs and CLK pins.
CLK[3..0]
The corner fast PLLs can also be driven through the global or regional clock
networks. The global or regional clock input to the fast PLL can be driven by an
output from another PLL, a pin-driven global or regional clock, or internally-
generated global signals.
Figure
Figure
2–42:
Global Clock [15..0]
2–43. See
CLK[7..4]
Figures 2–50
Note (1)
CLK[15..12]
Stratix Device Handbook, Volume 1
Global Clock [15..0]
and
2–51
for RCLK connections
Stratix Architecture
CLK[11..8]
2–75