EP1S80F1508C6 Altera, EP1S80F1508C6 Datasheet - Page 126
EP1S80F1508C6
Manufacturer Part Number
EP1S80F1508C6
Description
IC STRATIX FPGA 80K LE 1508-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S80F1508C6
Number Of Logic Elements/cells
79040
Number Of Labs/clbs
7904
Total Ram Bits
7427520
Number Of I /o
1203
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1508-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1441
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S80F1508C6
Manufacturer:
ALTERA
Quantity:
465
Part Number:
EP1S80F1508C6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1S80F1508C6N
Manufacturer:
ALTERA
Quantity:
5
Part Number:
EP1S80F1508C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
I/O Structure
Figure 2–65. Stratix IOE in DDR Input I/O Configuration
Notes to
(1)
(2)
(3)
2–112
Stratix Device Handbook, Volume 1
Column or Row
Interconnect
All input signals to the IOE can be inverted at the IOE.
This signal connection is only allowed on dedicated DQ function pins.
This signal is for dedicated DQS function pins only.
I/O Interconnect
Figure
[15..0]
2–65:
ioe_clk[7..0]
(1)
DQS Local
Bus (1), (2)
(1)
sclr
clkin
aclr/prn
Chip-Wide Reset
Enable Delay
Output Clock
Input Register
Input Register
Note (1)
D
ENA
CLRN/PRN
D
CLRN/PRN
ENA
Input Register Delay
Input Pin to
Q
Q
D
ENA
CLRN/PRN
To DQS Local
Latch
Bus (3)
Q
VCCIO
Altera Corporation
VCCIO
Optional
PCI Clamp
Bus-Hold
Circuit
July 2005
Programmable
Pull-Up
Resistor