EP4SE530H35C3 Altera, EP4SE530H35C3 Datasheet - Page 396
EP4SE530H35C3
Manufacturer Part Number
EP4SE530H35C3
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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10–62
Stratix IV Device Handbook Volume 1
User Watchdog Timer
1
1
The user watchdog timer prevents a faulty application configuration from stalling the
device indefinitely. The system uses the timer to detect functional errors after an
application configuration is successfully loaded into the Stratix IV device.
The user watchdog timer is a counter that counts down from the initial value loaded
into the remote system upgrade control register by the factory configuration. The
counter is 29 bits wide and has a maximum count value of 2
user watchdog timer value, specify only the most significant 12 bits. The granularity
of the timer setting is 2
10-MHz internal oscillator.
internal oscillator.
Table 10–18. 10-MHz Internal Oscillator Specifications
The user watchdog timer begins counting after the application configuration enters
device user mode. This timer must be periodically reloaded or reset by the application
configuration before the timer expires by asserting RU_nRSTIMER. If the application
configuration does not reload the user watchdog timer before the count expires, a
time-out signal is generated by the remote system upgrade dedicated circuitry. The
time-out signal tells the remote system upgrade circuitry to set the user watchdog
timer status bit (Wd) in the remote system upgrade status register and reconfigures the
device by loading the factory configuration.
To allow remote system upgrade dedicated circuitry to reset the watchdog timer, you
must assert the RU_nRSTIMER signal active for a minimum of 250 ns. This is equivalent
to strobing the reset_timer input of the ALTREMOTE_UPDATE megafunction high
for a minimum of 250 ns.
The user watchdog timer is not enabled during the configuration cycle of the device.
Errors during configuration are detected by the CRC engine. Also, the timer is
disabled for factory configurations. Functional errors should not exist in the factory
configuration because it is stored and validated during production and is never
updated remotely.
The user watchdog timer is disabled in factory configurations and during the
configuration cycle of the application configuration. It is enabled after the application
configuration enters user mode.
Note to
(1) These values are preliminary.
Minimum
Table
4.3
10–18:
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
17
cycles. The cycle time is based on the frequency of the
Table 10–18
Typical
5.3
lists the operating range of the 10-MHz
Maximum
(Note 1)
10
Dedicated Remote System Upgrade Circuitry
29
. When specifying the
April 2011 Altera Corporation
Units
MHz
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