EP2S180F1020C4 Altera, EP2S180F1020C4 Datasheet - Page 226
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EP2S180F1020C4
Manufacturer Part Number
EP2S180F1020C4
Description
IC STRATIX II FPGA 180K 1020FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S180F1020C4
Number Of Logic Elements/cells
179400
Number Of Labs/clbs
8970
Total Ram Bits
9383040
Number Of I /o
742
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
179400
# I/os (max)
742
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
179400
Ram Bits
9383040
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
For Use With
544-1701 - DSP PRO KIT W/SII EP2S180N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1415
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S180F1020C4
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S180F1020C4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2S180F1020C4N
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
EP2S180F1020C4N
Manufacturer:
ALTERA
Quantity:
748
High-Speed I/O Specifications
5–90
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
f
f
f
f
TCCS
SW
Output jitter
Output t
Output t
t
DPA run length
DPA jitter tolerance
DPA lock time
H S C L K
H S C L K
H S D R
H S D R D PA
DUTY
Table 5–91. High-Speed I/O Specifications for -5 Speed Grade
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
(data rate)
(clock frequency)
= f
R I S E
FA L L
Table
Symbol
H S D R
(DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
5–91:
/ W
W = 2 to 32 (LVDS, HyperTransport technology)
(3)
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only)
J = 4 to 10 (LVDS, HyperTransport technology)
J = 2 (LVDS, HyperTransport technology)
J = 1 (LVDS only)
All differential I/O standards
All differential I/O standards
All differential I/O standards
All differential I/O standards
Data channel peak-to-peak jitter
SPI-4
Parallel Rapid I/O
Miscellaneous
Table 5–91
grade Stratix II devices.
Standard
shows the high-speed I/O timing specifications for -5 speed
Conditions
0000000000
1111111111
00001111
10010000
10101010
01010101
Training
Pattern
Transition
Density
100%
10%
25%
50%
Notes
(1),
0.44
Min
150
150
256
256
256
256
256
150
440
16
16
(4)
(4)
45
-5 Speed Grade
-
(2)
Typ
50
Altera Corporation
6,400
Max
420
500
640
840
700
500
840
200
190
290
290
55
-
Number of
repetitions
April 2011
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
Unit
ps
ps
ps
ps
ps
UI
UI
%