EP2S180F1508C4 Altera, EP2S180F1508C4 Datasheet - Page 54
EP2S180F1508C4
Manufacturer Part Number
EP2S180F1508C4
Description
IC STRATIX II FPGA 180K 1508FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S180F1508C4
Number Of Logic Elements/cells
179400
Number Of Labs/clbs
8970
Total Ram Bits
9383040
Number Of I /o
1170
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1508-FBGA
For Use With
544-1701 - DSP PRO KIT W/SII EP2S180N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1416
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S180F1508C4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP2S180F1508C4ES
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2S180F1508C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S180F1508C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Digital Signal Processing Block
Figure 2–30. DSP Block Interface to Interconnect
2–46
Stratix II Device Handbook, Volume 1
C4 Interconnect
LAB
18
DSP Block to
LAB Row Interface
Block Interconnect Region
Direct Link Interconnect
from Adjacent LAB
36
16
A bus of 44 control signals feeds the entire DSP block. These signals
include clocks, asynchronous clears, clock enables, signed/unsigned
control signals, addition and subtraction control signals, rounding and
saturation control signals, and accumulator synchronous loads. The clock
signals are routed from LAB row clocks and are generated from specific
LAB rows at the DSP block interface.
Row Interface
36
12
Block
36 Inputs per Row
R4 Interconnect
16
Control
A[17..0]
B[17..0]
DSP Block
Row Structure
OA[17..0]
OB[17..0]
36 Outputs per Row
Direct Link Outputs
to Adjacent LABs
36
36
Altera Corporation
Direct Link Interconnect
from Adjacent LAB
May 2007
LAB