EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 7

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Stratix IV E ES Device Issues
March 2011 Altera Corporation
M144K Write with Dual-Port Dual-Clock Modes
Automatic Clock Switchover
CRC Error Detection Feature
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f
1
1
M144K RAM blocks in dual-port dual-clock modes may fail to operate correctly,
affecting applications such as DCFIFO memories, where data is transferred between
two separate clock domains.
If you are using Stratix IV E ES devices with the Quartus II software version 9.0, you
must recompile your design and manually avoid all use of M144K RAM blocks in
dual-port dual-clock modes. The Quartus II software version 9.0 SP1 will
automatically disable use of dual-port dual-clock modes in all M144K RAM blocks. In
both cases, your design’s usage of M9K RAM blocks may increase as a result.
This issue is fixed in production devices.
You can download a software patch to help with M144K RAM blocks in dual-port
dual-clock mode failure at:
http://www.altera.com/support/kdb/solutions/rd04092009_699.html
The PLL Automatic Clock Switchover feature may fail to operate correctly on Stratix
IV E ES devices when the two clocks are running different frequencies. If both clocks
are running at the same frequency, there is no impact to your design. The following
modes are affected:
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■
You may observe two possible issues:
■
■
Manual clock switchover mode operates correctly as expected and is not affected.
This issue is fixed in production devices.
The CRC Error Detection feature, when single event upset (SEU) detection is enabled,
may cause the MLAB RAM blocks to operate incorrectly in Stratix IV E ES devices.
Write operations in MLAB RAM blocks are affected with all CRC Error Detection
divisor settings.
The CRC Error Detection feature operates correctly as expected. FPGA configuration
bits are not affected by this issue.
Disabling the CRC Error Detection feature in your design compilation with the
Quartus II software will prevent this issue from occurring in ES devices.
This issue is fixed in production devices.
You can download a software patch to help with the CRC Error Detection feature
issue at:
Automatic
Automatic with Manual Override
Switchover from inclk0 to inclk1, even though inclk0 is active (and vice-versa)
clkbad[0,1] status signals may glitch, even if the input clocks are active
http://www.altera.com/support/kdb/solutions/rd04092009_699.html
Errata Sheet for Stratix IV E Devices
Page 7