XC3S500E-4CPG132I Xilinx Inc, XC3S500E-4CPG132I Datasheet - Page 139
![IC FPGA SPARTAN-3E 500K 132CSBGA](/photos/6/70/67095/pk373-cp132_sml.jpg)
XC3S500E-4CPG132I
Manufacturer Part Number
XC3S500E-4CPG132I
Description
IC FPGA SPARTAN-3E 500K 132CSBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4CPG132I
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
92
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
132-TFBGA, CSPBGA
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-4CPG132I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Table 99: CLB Distributed RAM Switching Characteristics
Table 100: CLB Shift Register Switching Characteristics
DS312-3 (v3.8) August 26, 2009
Product Specification
Clock-to-Output Times
Setup Times
Hold Times
Clock Pulse Width
Clock-to-Output Times
Setup Times
Hold Times
Clock Pulse Width
T
T
WPH
WPH
T
Symbol
Symbol
T
T
T
AH,
T
SHCKO
SRLDS
SRLDH
T
T
T
T
REG
WS
AS
DH
DS
, T
, T
T
WH
WPL
WPL
R
Time from the active edge at the CLK input to data
appearing on the distributed RAM output
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
Setup time of the F/G address inputs before the active
transition at the CLK input of the distributed RAM
Setup time of the write enable input before the active
transition at the CLK input of the distributed RAM
Hold time of the BX, BY data inputs after the active
transition at the CLK input of the distributed RAM
Hold time of the F/G address inputs or the write enable
input after the active transition at the CLK input of the
distributed RAM
Minimum High or Low pulse width at CLK input
Time from the active edge at the CLK input to data
appearing on the shift register output
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
Hold time of the BX or BY data input after the active
transition at the CLK input of the shift register
Minimum High or Low pulse width at CLK input
Description
Description
www.xilinx.com
0.40
0.46
0.34
0.13
0.88
0.41
0.14
0.88
Min
Min
0
-
-
-5
-5
DC and Switching Characteristics
Max
2.05
Max
3.62
-
-
-
-
-
-
-
-
-
0.46
0.52
0.40
0.15
1.01
0.46
0.16
1.01
Min
Min
0
-
-
-4
-4
Max
2.35
Max
4.16
-
-
-
-
-
-
-
-
-
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
139
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