XC3S500E-4VQG100I Xilinx Inc, XC3S500E-4VQG100I Datasheet - Page 11

IC FPGA SPARTAN-3E 500K 100-VQFP

XC3S500E-4VQG100I

Manufacturer Part Number
XC3S500E-4VQG100I
Description
IC FPGA SPARTAN-3E 500K 100-VQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet

Specifications of XC3S500E-4VQG100I

Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
66
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
100-TQFP
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC3S500E-4VQG100I
Manufacturer:
XILINX
Quantity:
2 360
Part Number:
XC3S500E-4VQG100I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S500E-4VQG100I
Manufacturer:
XILINX
0
DS312-2 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
IDDRIN1
IDDRIN2
OTCLK1
OTCLK2
ICLK1
ICLK2
IDDRIN1/IDDRIN2 signals shown with dashed lines connect to the adjacent IOB in a differential pair only, not to the FPGA fabric.
All IOB control and output path signals have an inverting polarity option wihtin the IOB.
TCE
OCE
REV
IQ1
ICE
IQ2
T1
T2
SR
O1
O2
T
I
R
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
SR
SR REV
SR
SR REV
SR
SR REV
REV
REV
REV
Q
Q
Q
Q
Q
Q
Figure 5: Simplified IOB Diagram
TFF1
TFF2
OFF1
OFF2
IFF1
IFF2
Programmable
Programmable
www.xilinx.com
DDR
MUX
DDR
MUX
Delay
Delay
Three-state Path
Input Path
Output Path
Program-
Output
mable
Driver
Single-ended Standards
LVCMOS, LVTTL, PCI
Differential Standards
using V REF
Functional Description
Pull-Up
Down
Pull-
Keeper
Latch
DS312-2_19_110606
V
Pin
I/O Pin
from
Adjacent
IOB
ESD
ESD
V
REF
CCO
I/O
Pin
11

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