XA3S500E-4FTG256I Xilinx Inc, XA3S500E-4FTG256I Datasheet - Page 35
![IC FPGA SPARTAN-3E 500K 256FTBGA](/photos/6/71/67101/pk053-256_sml.jpg)
XA3S500E-4FTG256I
Manufacturer Part Number
XA3S500E-4FTG256I
Description
IC FPGA SPARTAN-3E 500K 256FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3E XAr
Datasheet
1.XA3S100E-4VQG100I.pdf
(37 pages)
Specifications of XA3S500E-4FTG256I
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
190
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XA3S500E-4FTG256I
Manufacturer:
XILINX
Quantity:
7 208
Company:
Part Number:
XA3S500E-4FTG256I
Manufacturer:
Xilinx Inc
Quantity:
10 000
IEEE 1149.1/1553 JTAG Test Access Port Timing
Table 44: Timing for the JTAG Test Access Port
DS635 (v2.0) September 9, 2009
Product Specification
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
Hold Times
T
T
Clock Timing
T
T
F
TCKTDO
TDITCK
TMSTCK
TCKTDI
TCKTMS
CCH
CCL
TCK
The numbers in this table are based on the operating conditions set forth in
Symbol
R
The time from the falling transition on the TCK pin
to data appearing at the TDO pin
The time from the setup of data at the TDI pin to
the rising transition at the TCK pin
The time from the setup of a logic level at the TMS
pin to the rising transition at the TCK pin
The time from the rising transition at the TCK pin
to the point when data is last held at the TDI pin
The time from the rising transition at the TCK pin
to the point when a logic level is last held at the
TMS pin
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
Frequency of the TCK signal
Description
www.xilinx.com
Table
6.
Min
1.0
7.0
7.0
0
0
5
5
-
-4 Speed Grade
Max
11.0
25
-
-
-
-
-
-
Units
MHz
ns
ns
ns
ns
ns
ns
ns
35