XCS30XL-4TQG144C Xilinx Inc, XCS30XL-4TQG144C Datasheet - Page 57
![IC SPARTAN-XL FPGA 30K 144-TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XCS30XL-4TQG144C
Manufacturer Part Number
XCS30XL-4TQG144C
Description
IC SPARTAN-XL FPGA 30K 144-TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-XLr
Datasheet
1.XCS05XL-4VQG100C.pdf
(83 pages)
Specifications of XCS30XL-4TQG144C
Number Of Logic Elements/cells
1368
Number Of Labs/clbs
576
Total Ram Bits
18432
Number Of I /o
113
Number Of Gates
30000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1297
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCS30XL-4TQG144C
Manufacturer:
SIEMENS
Quantity:
2 000
Company:
Part Number:
XCS30XL-4TQG144C
Manufacturer:
XILINX
Quantity:
154
Part Number:
XCS30XL-4TQG144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (cont.)
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Timing
Single Port
DS060 (v1.8) June 26, 2008
Product Specification
Notes:
1.
DATA OUT
Write Operation
ADDRESS
WCLK (K)
DATA IN
Symbol
T
T
T
T
T
T
Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing
WODS
WCDS
WPDS
WSDS
ASDS
DSDS
WE
R
T
Clock K pulse width (active edge)
Address setup time before clock K
DIN setup time before clock K
WE setup time before clock K
All hold times after clock K
Data valid after clock K
Address write cycle time (clock K period)
ILO
(1)
T
T
T
WSS
DSS
ASS
T
WOS
OLD
Dual Port RAM
T
WPS
T
T
T
NEW
AHS
WHS
DHS
www.xilinx.com
T
ILO
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan-XL devices
and are expressed in nanoseconds unless otherwise noted.
DATA OUT
ADDRESS
WCLK (K)
DATA IN
Dual Port
Spartan and Spartan-XL FPGA Families Data Sheet
WE
16x1
16x1
16x1
16x1
16x1
16x1
16x1
Size
T
ILO
Min
7.7
3.1
1.3
1.7
1.4
0
-
T
T
T
DSDS
ASDS
WSDS
-5
Max
T
5.2
WODS
-
-
-
-
-
-
OLD
Min
8.4
3.6
1.5
2.0
1.6
0
-
-4
T
WPDS
Max
6.1
T
T
T
-
-
-
-
-
-
NEW
WHDS
T
AHDS
DHDS
DS060_34_011300
ILO
Units
ns
ns
ns
ns
ns
ns
ns
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