XA3S700A-4FGG400Q Xilinx Inc, XA3S700A-4FGG400Q Datasheet - Page 2

• Manufacturer Part Number: XA3S700A-4FGG400Q
• Description: IC FPGA SPARTAN-3A 700K 400-FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A XAr

Specifications of XA3S700A-4FGG400Q

• Number Of Logic Elements/cells: 13248
• Number Of Labs/clbs: 1472
• Total Ram Bits: 368640
• Number Of I /o: 311
• Number Of Gates: 700000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Key Feature Differences from Commercial XC Devices
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•
•
Table 1: Summary of XA Spartan-3A FPGA Attributes
Notes:
1.
Architectural Overview
The XA Spartan-3A family architecture consists of five
fundamental programmable functional elements:
•
•
•
•
2
XA3S200A
XA3S400A
XA3S700A
XA3S1400A 1400K
Device
AEC-Q100 device qualification and full production part
approval process (PPAP) documentation support
available in both extended temperature I- and
Q-Grades
Guaranteed to meet full electrical specification over the
T
XA Spartan-3A devices are available in the -4 speed
grade only
By convention, one Kb is equivalent to 1,024 bits.
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including several high-performance
differential standards. Double Data-Rate (DDR)
registers are included.
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
J
= –40°C to +125°C temperature range (Q-Grade)
System
Gates
200K
400K
700K
Logic Cells
Equivalent
13,248
25,344
4,032
8,064
Rows Columns
32
40
48
72
(One CLB = Four Slices)
16
24
32
40
CLB Array
1,472 5,888
2,816 11,264
CLBs
Total
448
896
www.xilinx.com
1,792
3,584
Slices
Total
•
•
•
•
•
•
Distributed
RAM bits
176K
PCI-66 is not supported in the XA Spartan-3A FPGA
product line
Platform Flash is not supported within the XA family
XA Spartan-3A devices are available in Pb-Free
packaging only.
MultiBoot is not supported in XA versions of this
product.
The XA Spartan-3A device must be power cycled prior
to reconfiguration.
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.These elements are organized as shown in
Figure
regular array of CLBs. Each device has two columns of
block RAM. Each RAM column consists of several
18-Kbit RAM blocks. Each block RAM is associated
with a dedicated multiplier. The DCMs are positioned in
the center with two at the top and two at the bottom of
the device. The XA3S700A and XA3S1400A add two
DCMs in the middle of the two columns of block RAM
and multipliers. The XA Spartan-3A family features a
rich network of routing that interconnect all five
functional elements, transmitting signals among them.
Each functional element has an associated switch
matrix that permits multiple connections to the routing.
28K
56K
92K
(1)
1. A dual ring of staggered IOBs surrounds a
288K
360K
360K
576K
Block
bits
RAM
(1)
Multipliers DCMs
Dedicated
16
20
20
32
DS681 (v1.1) February 3, 2009
4
4
8
8
Product Specification
Maximum
User I/O
195
311
372
375
Differential
Maximum
I/O Pairs
142
165
165
90
R