XC3SD1800A-5FG676C Xilinx Inc, XC3SD1800A-5FG676C Datasheet - Page 28
![SPARTAN-3ADSP FPGA 1800K 676FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC3SD1800A-5FG676C
Manufacturer Part Number
XC3SD1800A-5FG676C
Description
SPARTAN-3ADSP FPGA 1800K 676FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD1800A-5FG676C
Number Of Logic Elements/cells
37440
Number Of Labs/clbs
4160
Total Ram Bits
1548288
Number Of I /o
519
Number Of Gates
1800000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
For Use With
122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD1800A-5FG676C
Manufacturer:
XILINX
Quantity:
852
Company:
Part Number:
XC3SD1800A-5FG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3SD1800A-5FG676C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Three-State Output Propagation Times
Table 24: Timing for the IOB Three-State Path
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
Synchronous Output Enable/Disable Times
T
T
Asynchronous Output Enable/Disable Times
T
Set/Reset Times
T
T
IOCKHZ
IOCKON
GTS
IOSRHZ
IOSRON
Symbol
The numbers in this table are tested using the methodology presented in
Table 7
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from
(2)
(2)
and
Table
Time from the active transition at the OTCLK
input of the Three-state Flip-Flop (TFF) to when
the Output pin enters the high-impedance state
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
Time from asserting the Global Three State
(GTS) input on the STARTUP_SPARTAN3A
primitive to when the Output pin enters the
high-impedance state
Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state
Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data
10.
Description
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
LVCMOS25, 12 mA
output drive, Fast slew
rate
LVCMOS25, 12 mA
output drive, Fast slew
rate
LVCMOS25, 12 mA
output drive, Fast slew
rate
Conditions
Table 26
Table
25.
and are based on the operating conditions set forth in
Device
All
All
All
All
All
Speed Grade
Max
1.13
3.08
9.47
1.61
3.57
-5
10.36
Max
1.39
3.35
1.86
3.82
-4
Units
ns
ns
ns
ns
ns
28