XC3S5000-5FGG676C Xilinx Inc, XC3S5000-5FGG676C Datasheet - Page 11
![SPARTAN-3A FPGA 5M 676-FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC3S5000-5FGG676C
Manufacturer Part Number
XC3S5000-5FGG676C
Description
SPARTAN-3A FPGA 5M 676-FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S5000-5FGG676C
Number Of Logic Elements/cells
74880
Number Of Labs/clbs
8320
Total Ram Bits
1916928
Number Of I /o
489
Number Of Gates
5000000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
Package
676FBGA
Family Name
Spartan®-3
Device Logic Units
74880
Device System Gates
5000000
Maximum Internal Frequency
725 MHz
Typical Operating Supply Voltage
1.2 V
Ram Bits
1916928
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S5000-5FGG676C
Manufacturer:
SUSUMU
Quantity:
200 000
Company:
Part Number:
XC3S5000-5FGG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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DS099-2 (v2.5) December 4, 2009
Design Documentation Available
The functionality of the Spartan
described in the following documents. The topics covered in
each guide are listed below.
•
•
© 2003–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun-
tries. All other trademarks are the property of their respective owners.
DS099-2 (v2.5) December 4, 2009
Product Specification
UG331: Spartan-3 Generation FPGA User Guide
http://www.xilinx.com/support/documentation/
user_guides/ug331.pdf
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UG332: Spartan-3 Generation Configuration User
Guide
http://www.xilinx.com/support/documentation/
user_guides/ug332.pdf
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Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
Distributed RAM
SRL16 Shift Registers
Carry and Arithmetic Logic
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE
IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Configuration Overview
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Detailed Descriptions by Mode
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ISE iMPACT Programming Examples
®
Configuration Pins and Behavior
Bitstream Sizes
Master Serial Mode using Xilinx Platform Flash
PROM
Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
Software Design Tools
R
®
-3 FPGA family is
54
www.xilinx.com
0
Spartan-3 FPGA Family:
Functional Description
Product Specification
For specific hardware examples, please see the Spartan-3
FPGA Starter Kit board web page, which has links to
various design examples and the user guide.
•
•
Create a Xilinx MySupport user account and sign up to
receive automatic e-mail notification whenever this data
sheet or the associated user guides are updated.
•
Spartan-3 FPGA Starter Kit Board Page
http://www.xilinx.com/s3starter
UG130: Spartan-3 FPGA Starter Kit User Guide
http://www.xilinx.com/support/documentation/
boards_and_kits/ug130.pdf
Sign Up for Alerts on Xilinx MySupport
http://www.xilinx.com/support/answers/19380.htm
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