XC5VLX30-2FFG324C Xilinx Inc, XC5VLX30-2FFG324C Datasheet - Page 136
![IC FPGA VIRTEX-5 30K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-2FFG324C
Manufacturer Part Number
XC5VLX30-2FFG324C
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-2FFG324C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX30-2FFG324C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 4: Block RAM
136
Block RAM Timing Characteristics
Clock Event 1
The timing diagram in
without the optional output register. The timing for read-first and no-change modes are
similar. For timing using the optional output register, an additional clock latency appears
at the DO pin. These waveforms correspond to latch mode when the optional output
pipeline register is not used.
X-Ref Target - Figure 4-14
At time 0, the block RAM is disabled; EN (enable) is Low.
Read Operation
During a read operation, the contents of the memory at the address on the ADDR inputs
remain unchanged.
•
•
•
•
ADDR
** SRVAL = 0101
SSR
CLK
* Write Mode = "WRITE_FIRST"
WE
DO
T
the block RAM.
At time T
block RAM, enabling the memory for the READ operation that follows.
At time T
become stable at the DO pins of the block RAM.
Whenever EN is asserted, all address changes must meet the specified setup and hold
window. Asynchronous address changes can affect the memory content and block
RAM functionality in an unpredictable way.
EN
DI
RCCK_ADDR
Disabled
RCCK_EN
RCKO_DO
1
T RDCK_DI
T RCCK_ADDR
T RCCK_EN
T RCCK_WE
DDDD
before clock event 1, address 00 becomes valid at the ADDR inputs of
00
T RCKO_DO
Read
MEM (00)
Figure 4-14: Block RAM Timing Diagram
before clock event 1, enable is asserted High at the EN input of the
Figure 4-14
after clock event 1, the contents of the memory at address 00
www.xilinx.com
2
CCCC
0F
describes a single-port block RAM in write-first mode
Write
CCCC*
3
T RCCK_SSR
BBBB
7E
Read
MEM (7E)
4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
AAAA
8F
Reset
0101**
ug190_4_13_022207
5
0000
Disabled
20
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