XCV300-4FG456I Xilinx Inc, XCV300-4FG456I Datasheet - Page 21

• Manufacturer Part Number: XCV300-4FG456I
• Description: IC FPGA 2.5V I-TEMP 456-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™r

Specifications of XCV300-4FG456I

• Number Of Logic Elements/cells: 6912
• Number Of Labs/clbs: 1536
• Total Ram Bits: 65536
• Number Of I /o: 312
• Number Of Gates: 322970
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 456-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Abort
During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the cur-
rent packet command to be aborted. The device will remain
BUSY until the aborted operation has completed. Following
an abort, data is assumed to be unaligned to word bound-
DS003-2 (v2.8.1) December 9, 2002
Product Specification
R
and start-up sequences complete.
later FPGAs enter start-up phase
first FPGAs enter start-up phase
are released, DONE goes High
FPGA checks data using CRC
and pulls INIT Low on error.
clearing pass and releases
configuration memory.
Figure 17: SelectMAP Flowchart for Write Operation
FPGA starts to clear
When all DONE pins
FPGA makes a final
Once per bitstream,
INIT when finished.
releasing DONE.
releasing DONE.
If no errors,
If no errors,
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Apply Configuration Byte
Configuration Completed
aries, and the FPGA requires a new synchronization word
prior to accepting any new packets.
To initiate an abort during a write operation, de-assert
WRITE. At the rising edge of CCLK, an abort is initiated, as
shown in
Disable Data Source
Repeat Sequence A
Enter Data Source
Set WRITE = High
Set WRITE = Low
Set CS = High
Set CS = Low
End of Data?
Apply Power
Release INIT
PROGRAM
from Low
to High
Busy?
INIT?
Virtex™ 2.5 V Field Programmable Gate Arrays
Figure
High
Low
Yes
Yes
High
Low
18.
No
No
If used to delay
configuration
On first FPGA
On first FPGA
For any other FPGAs
Sequence A
ds003_17_090602
Module 2 of 4
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