XC5VLX30-3FF324C Xilinx Inc, XC5VLX30-3FF324C Datasheet - Page 348
![IC FPGA VIRTEX-5 30K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-3FF324C
Manufacturer Part Number
XC5VLX30-3FF324C
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-3FF324C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 7: SelectIO Logic Resources
348
ODDR VHDL and Verilog Templates
OLOGIC Timing Models
Timing Characteristics
The Libraries Guide includes templates for instantiation of the ODDR module in VHDL
and Verilog.
This section discusses all timing models associated with the OLOGIC block.
describes the function and control signals of the OLOGIC switching characteristics in the
Virtex-5 FPGA Data Sheet.
Table 7-15: OLOGIC Switching Characteristics
Figure 7-26
X-Ref Target - Figure 7-26
Setup/Hold
T
T
T
T
T
Clock to Out
T
T
OCE
CLK
ODCK
OOCECK
OSRCK
OTCK
OTCECK
OCKQ
RQ
OQ
SR
D1
/T
Symbol
/T
/T
/T
/T
OCKT
OCKD
OCKSR
illustrates the OLOGIC output register timing.
Figure 7-26: OLOGIC Output Register Timing Characteristics
OCKTCE
OCKOCE
1
T
T
D1/D2 pins Setup/Hold with respect to CLK
OCE pin Setup/Hold with respect to CLK
SR/REV pin Setup/Hold with respect to CLK
T1/T2 pins Setup/Hold with respect to CLK
TCE pin Setup/Hold with respect to CLK
CLK to OQ/TQ out
SR/REV pin to OQ/TQ out
ODCK
OOCECK
www.xilinx.com
T
OCKQ
2
Description
3
4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
T
OSRCK
Table 7-15
ug190_7_21_041206
5
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