XC5VLX30-2FF676I Xilinx Inc, XC5VLX30-2FF676I Datasheet - Page 356
![IC FPGA VIRTEX-5 30K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-2FF676I
Manufacturer Part Number
XC5VLX30-2FF676I
Description
IC FPGA VIRTEX-5 30K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-2FF676I
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
400
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
For Use With
HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 8: Advanced SelectIO Logic Resources
356
Bitslip Operation - BITSLIP
Clock Enable Inputs - CE1 and CE2
X-Ref Target - Figure 8-3
The BITSLIP pin performs a Bitslip operation synchronous to CLKDIV when asserted
(active High). Subsequently, the data seen on the Q1 to Q6 output ports will shift, as in a
barrel-shifter operation, one position every time Bitslip is invoked (DDR operation is
different from SDR). See
Each ISERDES_NODELAY block contains an input clock enable module
X-Ref Target - Figure 8-4
When NUM_CE = 1, the CE2 input is not used, and the CE1 input is an active High clock
enable connected directly to the input registers in the ISERDES_NODELAY. When
NUM_CE = 2, the CE1 and CE2 inputs are both used, with CE1 enabling the
ISERDES_NODELAY for ½ of a CLKDIV cycle, and CE2 enabling the
ISERDES_NODELAY for the other ½. The internal clock enable signal ICE shown in
Figure 8-4
Data Bits
CLKDIV_TX
Figure 8-3: Bit Ordering on Q1–Q6 Outputs of ISERDES_NODELAY Ports
CLKDIV
CLKDIV
C
D
A
B
E
F
RST
RST
CE1
CE2
is derived from the CE1 and CE2 inputs. ICE drives the clock enable inputs of
D1
D2
D3
D4
D5
D6
OSERDES
D
AR
D
AR
Figure 8-4: Input Clock Enable Module
BITSLIP Submodule
Q
www.xilinx.com
Q
Q
CE1R
CE2R
CLK_TX
F
E
D
for more details.
C
B
NUM_CE
CLK_RX
1
2
2
A
ICE
(To ISERDES Input Registers)
CLKDIV
D
ISERDES
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
X
0
1
Q1
Q2
Q3
Q4
Q5
Q6
UG190_8_04_110707
(Figure
CE2R
CE1R
CLKDIV_RX
UG190_8_03_100307
CE1
ICE
8-4).
E
D
C
B
A
F
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