XC5VLX50-1FF324I Xilinx Inc, XC5VLX50-1FF324I Datasheet - Page 81
![IC FPGA VIRTEX-5 50K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-1FF324I
Manufacturer Part Number
XC5VLX50-1FF324I
Description
IC FPGA VIRTEX-5 50K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FF324I
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50-1FF324I
Manufacturer:
TRIQUINT
Quantity:
12 000
Company:
Part Number:
XC5VLX50-1FF324I
Manufacturer:
XilinxInc
Quantity:
3 000
Table 97: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode
DS202 (v5.3) May 5, 2010
Product Specification
Example Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin,
situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values
shown in
T
T
PSDCMPLL_0
PHDCMPLL_0
Symbol
IOB Switching Characteristics, page
/
No Delay Global Clock and IFF
PLL in Source-Synchronous Mode
Description
32.
(2)
with DCM and
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
XC5VLX20T
XC5VLX30
XC5VLX30T
XC5VLX50
XC5VLX50T
XC5VLX85
XC5VLX85T
XC5VLX110
XC5VLX110T
XC5VLX155
XC5VLX155T
XC5VLX220
XC5VLX220T
XC5VLX330
XC5VLX330T
XC5VSX35T
XC5VSX50T
XC5VSX95T
XC5VSX240T
Device
(1)
Using DCM, PLL, and Global Clock Buffer. For
0.45
0.54
0.45
0.54
0.43
0.56
0.43
0.56
0.40
0.68
0.39
0.68
0.38
0.74
0.38
0.74
0.24
1.00
0.24
1.00
0.44
0.72
0.41
0.74
N/A
N/A
N/A
N/A
N/A
N/A
N/A
- 3
Speed Grade
0.32
0.56
0.46
0.54
0.46
0.54
0.44
0.56
0.44
0.56
0.42
0.68
0.42
0.68
0.41
0.74
0.41
0.74
0.29
1.00
0.29
1.00
0.36
1.23
0.36
1.23
0.34
1.40
0.36
1.40
0.46
0.72
0.43
0.74
0.41
0.98
0.35
1.47
- 2
0.33
0.63
0.46
0.57
0.46
0.57
0.44
0.59
0.44
0.59
0.42
0.71
0.42
0.71
0.41
0.78
0.41
0.78
0.33
1.04
0.33
1.04
0.38
1.27
0.38
1.27
0.37
1.46
0.38
1.46
0.46
0.75
0.43
0.77
0.41
1.02
0.38
1.53
- 1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
81