XC4VFX40-10FFG1152I Xilinx Inc, XC4VFX40-10FFG1152I Datasheet - Page 318
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XC4VFX40-10FFG1152I
Manufacturer Part Number
XC4VFX40-10FFG1152I
Description
IC FPGA VIRTEX-4 FX 40K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX40-10FFG1152I
Number Of Logic Elements/cells
41904
Number Of Labs/clbs
4656
Total Ram Bits
2654208
Number Of I /o
448
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1152-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 6: SelectIO Resources
318
Step 0: Calculate the SSO Allowance
SSO Allowance =
(L
(V
SSO Allowance =
(1.0 nH/1.1 nH)
(600 mV/(((22
SSO Allowance = 75.4%
Step 1: Calculate the SSO for Each Individual Bank for Bank 1
Ensure the SSO for each bank does not exceed 100%.
Bank1 SSO:50.9% < 100%
Bank2 SSO:50.9% < 100%
Bank3 SSO:0%< 100%
Bank4 SSO:60% < 100%
Bank5 SSO: 35% < 100%
Bank6 SSO:40% < 100%
Bank7 SSO:15% < 100%
Bank8 SSO:30% < 100%
Bank9 SSO:12% < 100%
Bank10 SSO:22% < 100%
Bank11 SSO:80% < 100%
Bank12 SSO:0% < 100%
Bank13 SSO:5% < 100%
Bank14 SSO:60% < 100%
OK!
If the SSO of any bank exceeds 100%, apply ground bounce reduction techniques to the
bank until the SSO of all individual banks is less than 100%.
Step 2: Calculate the Adjacent Bank SSO Average for All Adjacent Bank Pairs
Ensure the adjacent bank averages do not exceed 105% of the SSO allowance.
First, calculate the adjacent bank SSO average for Banks 7 and 11, and check against 105%
of SSO allowance.
Adjacent Bank SSO Average 7 - 11 =
(SSO of bank 7 + SSO of bank 11)/2 = (15% + 80%)/2 = 47.5%
SSO allowance
= 79.2% > 47.5%
OK!
Then calculate adjacent bank SSO average for all adjacent bank pairs. If the average SSO of
two adjacent banks exceeds 105% of the SSO allowance, apply ground bounce reduction
NOM
NOISE_NOM
/L
DES
) × (V
/(((C
×
×
pF
NOISE_DES
×
LOAD_DES
105% > adjacent bank SSO average 7 - 11
(550 mV/600 mV)
–
15 pF)
/V
www.xilinx.com
– C
NOISE_NOM
×
LOAD_NOM
9 mV/pF) + 600 mV))
×
) ×
) × V
COEFF
) + V
NOISE_NOM
UG070 (v2.6) December 1, 2008
)
Virtex-4 FPGA User Guide
R
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