XC4VFX40-11FFG1152C Xilinx Inc, XC4VFX40-11FFG1152C Datasheet - Page 360
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XC4VFX40-11FFG1152C
Manufacturer Part Number
XC4VFX40-11FFG1152C
Description
IC FPGA VIRTEX-4 FX 40K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX40-11FFG1152C
Number Of Logic Elements/cells
41904
Number Of Labs/clbs
4656
Total Ram Bits
2654208
Number Of I /o
448
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Price
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Part Number:
XC4VFX40-11FFG1152C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 7: SelectIO Logic Resources
360
Timing Characteristics
Figure 7-26
Clock Event 1
•
•
Clock Event 4
At time T
case) becomes valid-High, resetting the output register and reflected at the Q output at
time T
CE
SR
D1
Q
C
At time T
High at the CE input of the output register, enabling the output register for incoming
data.
At time T
input of the output register and is reflected at the Q output at time T
Event 1.
RQ
OSRCK
after Clock Event 4.
illustrates the OLOGIC output register timing.
Figure 7-26: OLOGIC Output Register Timing Characteristics
OOCECK
ODCK
before Clock Event 4, the SR signal (configured as synchronous reset in this
before Clock Event 1, the output signal becomes valid-High at the D1
1
before Clock Event 1, the output clock enable signal becomes valid-
T
T
ODCK
OOCECK
www.xilinx.com
T
OCKQ
2
3
UG070 (v2.6) December 1, 2008
4
Virtex-4 FPGA User Guide
T
OSRCK
OCKQ
ug070_7_26_080204
after Clock
5
R
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