XC6VCX75T-1FFG484I Xilinx Inc, XC6VCX75T-1FFG484I Datasheet - Page 35
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XC6VCX75T-1FFG484I
Manufacturer Part Number
XC6VCX75T-1FFG484I
Description
IC FPGA VIRTEX 6 74K 484FFGBGA
Manufacturer
Xilinx Inc
Series
Virtex™ 6 CXTr
Datasheet
1.XC6VCX75T-1FFG484C.pdf
(52 pages)
Specifications of XC6VCX75T-1FFG484I
Number Of Logic Elements/cells
74496
Number Of Labs/clbs
5820
Total Ram Bits
5750784
Number Of I /o
240
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC6VCX75T-1FFG484I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 47: CLB Switching Characteristics (Cont’d)
DS153 (v1.6) February 11, 2011
Product Specification
Notes:
1.
2.
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Sequential Delays
T
T
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
T
T
T
T
T
Set/Reset
T
T
T
F
AXCY
BXB
BXD
CXB
CXD
DXD
OPCYA
OPCYB
OPCYC
OPCYD
BXCY
CXCY
DXCY
BYP
CINA
CINB
CINC
CIND
CKO
SHCKO
DICK
CECK_CLB
CKCE_CLB
SRCK
CINCK
SRMIN
RQ
CEO
TOG
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0”
is listed, there is no positive hold time.
These items are of interest for Carry Chain applications.
/T
/T
Symbol
/T
CKDI
CKSR
CKCIN
/
BX inputs to BMUX output
BX inputs to DMUX output
CX inputs to CMUX output
CX inputs to DMUX output
DX inputs to DMUX output
An input to COUT output
Bn input to COUT output
Cn input to COUT output
Dn input to COUT output
AX input to COUT output
BX input to COUT output
CX input to COUT output
DX input to COUT output
CIN input to COUT output
CIN input to AMUX output
CIN input to BMUX output
CIN input to CMUX output
CIN input to DMUX output
Clock to AQ – DQ outputs
Clock to AMUX – DMUX outputs
A – D input to CLK on A – D Flip Flops
CE input to CLK on A – D Flip Flops
SR input to CLK on A – D Flip Flops
CIN input to CLK on A – D Flip Flops
SR input minimum pulse width
Delay from SR input to AQ – DQ flip-flops
Delay from CE input to AQ – DQ flip-flops
Toggle frequency (for export control)
Description
www.xilinx.com
0.32/–0.01
0.52/–0.08
0.43/0.20
0.24/0.17
1098.00
0.39
0.50
0.34
0.40
0.38
0.42
0.42
0.35
0.33
0.33
0.28
0.20
0.19
0.08
0.28
0.29
0.30
0.33
0.39
0.47
0.97
0.68
0.59
-2
Virtex-6 CXT Family Data Sheet
Speed Grade
0.37/–0.01
0.60/–0.08
0.50/0.23
0.27/0.19
1098.00
0.45
0.58
0.38
0.45
0.44
0.47
0.47
0.39
0.37
0.38
0.32
0.23
0.22
0.32
0.34
0.34
0.38
0.44
0.54
0.97
0.78
0.67
0.09
-1
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
MHz
35