XC6VCX75T-2FFG484I Xilinx Inc, XC6VCX75T-2FFG484I Datasheet - Page 45
![no-image](/images/no-image-200.jpg)
XC6VCX75T-2FFG484I
Manufacturer Part Number
XC6VCX75T-2FFG484I
Description
IC FPGA VIRTEX 6 74K 484FFGBGA
Manufacturer
Xilinx Inc
Series
Virtex™ 6 CXTr
Datasheet
1.XC6VCX75T-1FFG484C.pdf
(52 pages)
Specifications of XC6VCX75T-2FFG484I
Number Of Logic Elements/cells
74496
Number Of Labs/clbs
5820
Total Ram Bits
5750784
Number Of I /o
240
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC6VCX75T-2FFG484I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 55: Regional Clock Switching Characteristics (BUFR)
Table 56: Horizontal Clock Buffer Switching Characteristics (BUFH)
MMCM Switching Characteristics
Table 57: MMCM Specification
DS153 (v1.6) February 11, 2011
Product Specification
T
T
T
Maximum Frequency
F
T
T
Maximum Frequency
F
F
F
F
F
F
F
F
F
F
BRCKO_O
BRCKO_O_BYP
BRDO_O
MAX
BHCKO_O
BHCCK_CE
MAX
INMAX
INMIN
INJITTER
INDUTY
MIN_PSCLK
MAX_PSCLK
VCOMIN
VCOMAX
BANDWIDTH
Symbol
Symbol
Symbol
/T
BHCKC_CE
Maximum Input Clock Frequency
Minimum Input Clock Frequency
Maximum Input Clock Period Jitter
Allowable Input Duty Cycle: 10—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum Dynamic Phase Shift Clock Frequency
Maximum Dynamic Phase Shift Clock Frequency
Minimum MMCM VCO Frequency
Maximum MMCM VCO Frequency
Low MMCM Bandwidth at Typical
High MMCM Bandwidth at Typical
Clock to out delay from I to O
Clock to out delay from I to O with Divide Bypass attribute set
Propagation delay from CLR to O
Regional clock tree (BUFR)
BUFH delay from I to O
CE pin Setup and Hold
Horizontal clock buffer (BUFH)
Description
Description
Description
www.xilinx.com
(1)
(2)
(2)
< 20% of clock input period or 1 ns
1200
0.01
1.00
4.00
450
700
600
10
-2
Speed Grade
Virtex-6 CXT Family Data Sheet
0.05/0.05
25/75
30/70
35/65
40/60
45/55
Max
0.13
0.75
0.75
0.75
0.75
0.37
0.37
0.37
0.37
0.83
700
300
-2
-2
Speed Grade
Speed Grade
1200
0.01
1.00
4.00
700
450
600
10
-1
0.05/0.05
0.13
0.75
0.75
0.75
0.75
0.37
0.37
0.37
0.37
0.83
700
300
-1
-1
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Units
Units
MHz
MHz
%
%
%
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45