XC5VSX50T-1FF665I Xilinx Inc, XC5VSX50T-1FF665I Datasheet - Page 24
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XC5VSX50T-1FF665I
Manufacturer Part Number
XC5VSX50T-1FF665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-1FF665I
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX50T-1FF665I
Manufacturer:
XILINX
Quantity:
133
Company:
Part Number:
XC5VSX50T-1FF665I
Manufacturer:
Xilinx Inc
Quantity:
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Company:
Part Number:
XC5VSX50T-1FF665I0750
Manufacturer:
XC
Quantity:
1 238
Table 46: GTX_DUAL Tile Transmitter Switching Characteristics (Cont’d)
Table 47: GTX_DUAL Tile Receiver Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
4.
SJ Jitter Tolerance
Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTX_DUAL sites.
Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations.
PLL frequency at 1.6 GHz and OUTDIV = 1.
GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed.
T
R
R
RXELECIDLE
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
Symbol
XOOBVDPP
Symbol
F
XPPMTOL
R
D
D
D
T
T
T
D
D
R
T
T
GTXRX
T
D
T
D
XSST
J3.75
J3.2L
J1.25
J3.75
J3.2L
J1.25
J750
J750
J150
J150
J3.2
J2.5
XRL
J3.2
J2.5
4.25
3.75
3.2L
1.25
6.5
5.0
3.2
2.5
(3)
Serial data rate
TIme for RXELECIDLE to
respond to loss or
restoration of data
OOB detect threshold
peak-to-peak
Receiver spread-spectrum
tracking
Run length (CID)
Data/REFCLK PPM offset
tolerance
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)(4)
(2)(4)
Description
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(2)
(2)
(2)
(2)
(2)
(2)(4)
(2)(4)
Description
RX oversampler not enabled
RX oversampler enabled
OOBDETECT_THRESHOLD = 110
OOBDETECT_THRESHOLD = 110
Modulated @ 33 KHz
Internal AC capacitor bypassed
CDR 2
CDR 2
6.5 Gb/s
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.2 Gb/s
3.2 Gb/s
2.5 Gb/s
1.25 Gb/s
www.xilinx.com
nd
nd
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(5)
-order loop disabled
-order loop enabled
3.2 Gb/s
Condition
3.75 Gb/s
1.25 Gb/s
750 Mb/s
150 Mb/s
3.2 Gb/s
2.5 Gb/s
(3)
Min
–5000
–2000
–200
0.75
0.15
0.44
0.44
0.44
0.44
0.45
0.45
0.50
0.50
Min
55
Typ
Typ
F
GTXMAX
Max
0.34
0.16
0.20
0.10
0.36
0.16
0.20
0.08
0.15
0.06
0.10
0.03
0.02
0.01
2000
Max
0.75
135
512
200
75
0
Units
Units
Gb/s
Gb/s
ppm
ppm
ppm
mV
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
ns
UI
UI
UI
UI
UI
UI
UI
UI
UI
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