XC5VLX85T-3FF1136C Xilinx Inc, XC5VLX85T-3FF1136C Datasheet - Page 379
XC5VLX85T-3FF1136C
Manufacturer Part Number
XC5VLX85T-3FF1136C
Description
IC FPGA VIRTEX-5 85K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX85T-3FF1136C
Number Of Logic Elements/cells
82944
Number Of Labs/clbs
6480
Total Ram Bits
3981312
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Part Number:
XC5VLX85T-3FF1136C
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Timing Characteristics of 8:1 DDR Serialization
Figure 8-18
example, a second OSERDES is required to achieve an 8:1 serialization. The two OSERDES
are connected and configured using the methods described in
page
remaining two bits are connected to D3–D4 of the slave OSERDES.
X-Ref Target - Figure 8-18
Clock Event 1
On the rising edge of CLKDIV, the word ABCDEFGH is driven from the FPGA logic to the
D1–D6 inputs of the master OSERDES and D3–D4 of the slave OSERDES (after some
propagation delay).
Clock Event 2
On the rising edge of CLKDIV, the word ABCDEFGH is sampled into the master and slave
OSERDES from the D1–D6 and D3–D4 inputs, respectively.
Clock Event 3
The data bit A appears at OQ four CLK cycles after ABCDEFGH is sampled into the
OSERDES. This latency is consistent with the
OSERDES latency of four CLK cycles.
Master.D1
Master.D2
Master.D3
Master.D4
Master.D5
Master.D6
Slave.D3
Slave.D4
375. Six of the eight bits are connected to D1–D6 of the master OSERDES while the
CLKDIV
CLK
OQ
Figure 8-18: OSERDES Data Flow and Latency in 8:1 DDR Mode
illustrates the timing of an 8:1 DDR data serialization. In contrast to the 2:1 SDR
Event 1
Clock
www.xilinx.com
Output Parallel-to-Serial Logic Resources (OSERDES)
G
A
B
C
D
E
F
H
Event 2
Clock
Table 8-10
M
N
O
K
L
P
J
I
listing of a 8:1 DDR mode
Event 3
Clock
OSERDES Width Expansion,
A B C D E F G H I
UG190_8_18_100307
Event 4
Clock
379
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