XC6VCX240T-1FFG784I Xilinx Inc, XC6VCX240T-1FFG784I Datasheet - Page 47

• Manufacturer Part Number: XC6VCX240T-1FFG784I
• Description: IC FPGA VIRTEX 6 241K 784FFGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX240T-1FFG784I

• Number Of Logic Elements/cells: 241152
• Number Of Labs/clbs: 18840
• Total Ram Bits: 15335424
• Number Of I /o: 400
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 784-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-6 CXT Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in
Table 58: Global Clock Input to Output Delay Without MMCM
Table 59: Global Clock Input to Output Delay With MMCM
Table 60: Clock-Capable Clock Input to Output Delay With MMCM
DS153 (v1.6) February 11, 2011
Product Specification
Notes:
1.
Notes:
1.
2.
Notes:
1.
2.
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without MMCM.
T
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM.
T
LVCMOS25 Clock-capable Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM.
T
ICKOF
ICKOFMMCMGC
ICKOFMMCMCC
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
MMCM output jitter is already included in the timing calculation.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
MMCM output jitter is already included in the timing calculation.
Symbol
Symbol
Symbol
Table
58. Values are expressed in nanoseconds unless otherwise noted.
Global Clock input and OUTFF without MMCM
Global Clock Input and OUTFF with MMCM
Clock-capable Clock Input and OUTFF with
MMCM
Description
Description
Description
www.xilinx.com
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
Device
Device
Device
Virtex-6 CXT Family Data Sheet
5.88
6.00
6.13
6.13
2.77
2.78
2.78
2.79
2.63
2.65
2.65
2.65
-2
-2
-2
Speed Grade
Speed Grade
Speed Grade
5.88
6.00
6.13
6.13
2.77
2.78
2.78
2.79
2.63
2.65
2.65
2.65
-1
-1
-1
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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