XC5VLX110-2FFG1153I Xilinx Inc, XC5VLX110-2FFG1153I Datasheet - Page 190
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XC5VLX110-2FFG1153I
Manufacturer Part Number
XC5VLX110-2FFG1153I
Description
IC FPGA VIRTEX-5 110K 1153FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110-2FFG1153I
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
4718592
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1153-BBGA, FCBGA
For Use With
HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 5: Configurable Logic Blocks (CLBs)
190
Read Only Memory (ROM)
Shift Registers (Available in SLICEM only)
Distributed RAM Data Flow
Synchronous Write Operation
The synchronous write operation is a single clock-edge operation with an active-High
write-enable (WE) feature. When WE is High, the input (D) is loaded into the memory
location at address A.
Asynchronous Read Operation
The output is determined by the address A (for single-port mode output/SPO output of
dual-port mode), or address DPRA (DPO output of dual-port mode). Each time a new
address is applied to the address pins, the data value in the memory location of that
address is available on the output after the time delay to access the LUT. This operation is
asynchronous and independent of the clock signal.
Distributed RAM Summary
•
•
•
•
Each function generator in SLICEMs and SLICELs can implement a 64 x 1-bit ROM. Three
configurations are available: ROM64x1, ROM128x1, and ROM256x1. ROM contents are
loaded at each device configuration.
ROM configuration.
Table 5-6: ROM Configuration
A SLICEM function generator can also be configured as a 32-bit shift register without using
the flip-flops available in a slice. Used in this way, each LUT can delay serial data
anywhere from one to 32 clock cycles. The shiftin D (DI1 LUT pin) and shiftout Q31 (MC31
LUT pin) lines cascade LUTs to form larger shift registers. The four LUTs in a SLICEM are
thus cascaded to produce delays up to 128 clock cycles. It is also possible to combine shift
registers across more than one SLICEM. Note that there are no direct connections between
slices to form longer shift registers, nor is the MC31 output at LUT B/C/D available. The
resulting programmable delays can be used to balance the timing of data pipelines.
Applications requiring delay or latency compensation use these shift registers to develop
efficient designs. Shift registers are also useful in synchronous FIFO and content
addressable memory (CAM) designs.
The write operation is synchronous with a clock input (CLK) and an optional clock enable
(CE). A dynamic read access is performed through the 5-bit address bus, A[4:0]. The LSB of
the LUT is unused and the software automatically ties it to a logic High. The configurable
shift registers cannot be set or reset. The read is asynchronous; however, a storage element
Single-port and dual-port modes are available in SLICEMs.
A write operation requires one clock edge.
Read operations are asynchronous (Q output).
The data input has a setup-to-clock timing specification.
128 x 1
256 x 1
64 x 1
ROM
www.xilinx.com
Table 5-6
shows the number of LUTs occupied by each
Number of LUTs
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
1
2
4
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