XC5VSX95T-1FFG1136C Xilinx Inc, XC5VSX95T-1FFG1136C Datasheet - Page 350
![IC FPGA VIRTEX-5 95K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-1FFG1136C
Manufacturer Part Number
XC5VSX95T-1FFG1136C
Description
IC FPGA VIRTEX-5 95K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-1FFG1136C
Total Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
No. Of Logic Blocks
7360
No. Of Macrocells
95000
Family Type
Virtex-5
No. Of Speed Grades
1
No. Of I/o's
640
Clock Management
DCM, PLL
Core Supply
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 7: SelectIO Logic Resources
350
Clock Event 9
At time T
synchronous reset in this case) becomes valid-High resetting ODDR register, reflected at
the OQ output at time T
and resetting ODDR register, reflected at the OQ output at time T
(no change at the OQ output in this case).
Figure 7-28
X-Ref Target - Figure 7-28
Clock Event 1
•
•
Clock Event 2
•
Figure 7-29
in opposite edge mode. For other modes add the appropriate latencies as shown in
Figure 7-4, page
CLK
TCE
SR
TQ
T1
At time T
High at the TCE input of the 3-state register, enabling the 3-state register for incoming
data.
At time T
input of the 3-state register, returning the pad to high-impedance at time T
Clock Event 1.
At time T
in this case) becomes valid-High, resetting the 3-state register at time T
Event 2.
OSRCK
T
OCKQ
illustrates the OLOGIC 3-state register timing.
Figure 7-28: OLOGIC 3-State Register Timing Characteristics
illustrates IOB DDR 3-state register timing. This example is shown using DDR
OTCECK
OTCK
OSRCK
before Clock Event 9 (rising edge of CLK), the SR signal (configured as
321.
1
before Clock Event 1 the 3-state signal becomes valid-High at the T
before Clock Event 2, the SR signal (configured as synchronous reset
before Clock Event 1, the 3-state clock enable signal becomes valid-
T
T
OTCK
OTCECK
RQ
www.xilinx.com
after Clock Event 9 (no change at the OQ output in this case)
2
T
OSRCK
T
RQ
3
4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
RQ
after Clock Event 10
RQ
UG190_7_23_041106
5
after Clock
OCKQ
after
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