XCV1600E-7FG680I Xilinx Inc, XCV1600E-7FG680I Datasheet - Page 69
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XCV1600E-7FG680I
Manufacturer Part Number
XCV1600E-7FG680I
Description
IC FPGA 1.8V I-TEMP 680-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheet
1.XCV200E-6CS144C.pdf
(233 pages)
Specifications of XCV1600E-7FG680I
Number Of Logic Elements/cells
34992
Number Of Labs/clbs
7776
Total Ram Bits
589824
Number Of I /o
512
Number Of Gates
2188742
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
680-LBGA Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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IOB Output Switching Characteristics,
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in
DS022-3 (v2.9.2) March 14, 2003
Production Product Specification
Notes:
1.
2.
Propagation Delays
O input to Pad
O input to Pad via transparent latch
3-State Delays
T input to Pad high-impedance (Note 2)
T input to valid data on Pad
T input to Pad high-impedance via transparent
latch (Note 2)
T input to valid data on Pad via transparent latch
GTS to Pad high impedance (Note 2)
Sequential Delays
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Clock CLK to Pad
Clock CLK to Pad high-impedance (synchronous)
(Note 2)
Clock CLK to valid data on Pad (synchronous)
Setup and Hold Times before/after Clock CLK
O input
OCE input
SR input (OFF)
3-State Setup Times, T input
3-State Setup Times, TCE input
3-State Setup Times, SR input (TFF)
Set/Reset Delays
SR input to Pad (asynchronous)
SR input to Pad high-impedance (asynchronous)
(Note 2)
SR input to valid data on Pad (asynchronous)
GSR to Pad
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
3-state turn-off delays should not be adjusted.
R
Description
(2)
IOB Output Switching Characteristics Standard Adjustments, page
T
T
T
T
IOOCECK
IOSRCKO
IOTCECK
IOSRCKT
T
T
Figure 1
IOOCK
IOTCK
T
T
T
T
T
Symbol
T
T
www.xilinx.com
T
T
T
T
T
IOTLPON
IOTLPHZ
1-800-255-7778
T
IOGSRQ
IOCKON
IOSRON
IOCKHZ
IOSRHZ
T
IOCKP
IOSRP
IOOLP
IOTHZ
IOTON
T
T
IOOP
GTS
CH
CL
/ T
/ T
/ T
/ T
/ T
/ T
IOCKT
IOCKTCE
IOCKO
IOCKOCE
IOCKOSR
IOCKTSR
0.43 / 0
0.28 / 0
0.40 / 0
0.26 / 0
0.30 / 0
0.38 / 0
Virtex™-E 1.8 V Field Programmable Gate Arrays
1.04
1.24
0.73
1.13
0.86
1.26
1.94
0.56
0.56
0.97
0.77
1.17
1.30
1.08
1.48
3.88
Min
0.55 / 0.01
0.51 / 0
0.9 / 0
0.8 / 0
0.6 / 0
0.8 / 0
Speed Grade
2.5
2.9
1.5
2.7
1.8
3.0
4.1
1.2
1.2
2.4
1.6
2.8
3.1
2.2
3.4
7.6
-8
1.0 / 0
0.7 / 0
0.6 / 0
0.7 / 0
0.9 / 0
0.9 / 0
2.7
3.1
1.7
2.9
2.0
3.2
4.6
1.3
1.3
2.8
2.0
3.2
3.3
2.4
3.7
8.5
-7
(1)
1.1 / 0
0.7 / 0
0.7 / 0
0.8 / 0
1.0 / 0
1.0 / 0
2.9
3.4
1.9
3.1
2.2
3.4
4.9
1.4
1.4
2.9
2.2
3.4
3.5
2.7
3.9
9.7
-6
10.
Module 3 of 4
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
Units
9
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