XC4VFX100-12FFG1517C Xilinx Inc, XC4VFX100-12FFG1517C Datasheet - Page 34
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XC4VFX100-12FFG1517C
Manufacturer Part Number
XC4VFX100-12FFG1517C
Description
IC FPGA VIRTEX-4FX 100K 1517FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX100-12FFG1517C
Number Of Logic Elements/cells
94896
Number Of Labs/clbs
10544
Total Ram Bits
6930432
Number Of I /o
768
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC4VFX100-12FFG1517C
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Xilinx Inc
Quantity:
10 000
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Chapter 1: Clock Resources
34
In
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•
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BUFGMUX_1 is rising edge sensitive and held at High prior to input switch.
illustrates the timing diagram for BUFGMUX_1. A LOC constraint is available for
BUFGMUX and BUFGMUX_1.
In
•
•
•
•
•
•
Figure
Figure
The current clock is I0.
S is activated High.
If I0 is currently High, the multiplexer waits for I0 to deassert Low.
Once I0 is Low, the multiplexer output stays Low until I1 transitions High to Low.
When I1 transitions from High to Low, the output switches to I1.
If the setup/hold times are met, no glitches or short pulses can appear on the output.
The current clock is I0.
S is activated High.
If I0 is currently Low, the multiplexer waits for I0 to be asserted High.
Once I0 is High, the multiplexer output stays High until I1 transitions Low to High.
When I1 transitions from Low to High, the output switches to I1.
If the setup/hold times are met, no glitches or short pulses can appear on the output.
1-9:
1-10:
Figure 1-10: BUFGMUX_1 Timing Diagram
I0
I1
S
O
www.xilinx.com
T
BCCKO_O
T
BCCCK_CE
UG070_1_10_082504
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
Figure 1-10
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