XC5VLX220T-1FFG1738I Xilinx Inc, XC5VLX220T-1FFG1738I Datasheet - Page 363
![IC FPGA VIRTEX-5 220K 1738FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX220T-1FFG1738I
Manufacturer Part Number
XC5VLX220T-1FFG1738I
Description
IC FPGA VIRTEX-5 220K 1738FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220T-1FFG1738I
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Total Ram Bits
7815168
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1738-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number:
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Quantity:
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Part Number:
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Manufacturer:
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Quantity:
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ISERDES Latencies
ISERDES Timing Model and Parameters
When the ISERDES interface type is MEMORY, the latency through the OCLK stage is one
CLKDIV cycle. However, the total latency through the ISERDES depends on the phase
relationship between the CLK and the OCLK clock inputs. When the ISERDES interface
type is NETWORKING, the latency is two CLKDIV cycles. See
Figure 8-13, page 369
cycle of latency in networking mode (compared to memory mode) is due to the Bitslip
submodule.
Table 8-4
characteristics in the Virtex-5 FPGA Data Sheet.
Table 8-4: ISERDES Switching Characteristics
Setup/Hold for Control Lines
T
T
T
Setup/Hold for Data Lines
T
T
Sequential Delay
T
ISCCK_BITSLIP
ISCCK_CE
ISCCK_CE
ISDCK_D
ISDCK_DDR
ISCKO_Q
describes the function and control signals of the ISERDES switching
/ T
/T
/T
/ T
Symbol
ISCKD_D
ISCKC_CE
ISCKC_CE
/ T
ISCKD_DDR
ISCKC_BITSLIP
for a visualization of latency in networking mode. The extra CLKDIV
www.xilinx.com
Input Serial-to-Parallel Logic Resources (ISERDES)
BITSLIP pin Setup/Hold with respect to CLKDIV
CE pin Setup/Hold with respect to CLK (for CE1)
CE pin Setup/Hold with respect to CLKDIV (for CE2)
D pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK at DDR mode
D pin Setup/Hold with respect to CLK at DDR mode
D pin Setup/Hold with respect to CLK at DDR mode
CLKDIV to Out at Q pins
Description
Figure 8-12, page 368
and
363
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