XC5VLX220-2FF1760I Xilinx Inc, XC5VLX220-2FF1760I Datasheet - Page 347
XC5VLX220-2FF1760I
Manufacturer Part Number
XC5VLX220-2FF1760I
Description
IC FPGA VIRTEX-5 220K 1760FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220-2FF1760I
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Total Ram Bits
7077888
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1760-BBGA, FCBGA
For Use With
HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX220-2FF1760I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Output DDR Primitive (ODDR)
Clock Forwarding
Output DDR can forward a copy of the clock to the output. This is useful for propagating
a clock and DDR data with identical delays, and for multiple clock generation, where every
clock load has a unique clock driver. This is accomplished by tying the D1 input of the
ODDR primitive High, and the D2 input Low. Xilinx recommends using this scheme to
forward clocks from the FPGA fabric to the output pins.
Figure 7-25
signals.
ODDR primitive.
X-Ref Target - Figure 7-25
Table 7-13: ODDR Port Signals
Table 7-14: ODDR Attributes
Q
C
CE
D1 and D2
R
S
DDR_CLK_EDGE
INIT
SRTYPE
Attribute Name
Name
Port
Table 7-14
shows the ODDR primitive block diagram.
Data output (DDR)
Clock input port
Clock enable port
Data inputs
Reset
Set
describes the various attributes available and default values for the
Function
Figure 7-25: ODDR Primitive Block Diagram
Sets the ODDR mode of operation with
respect to clock edge
Sets the initial value for Q port
Set/Reset type with respect to clock (C)
www.xilinx.com
CE
D1
D2
C
ODDR register output.
The CLK pin represents the clock input pin.
CE represents the clock enable pin. When asserted Low,
this port disables the output clock on port Q.
ODDR register inputs.
Synchronous/Asynchronous reset pin. Reset is asserted
High.
Synchronous/Asynchronous set pin. Set is asserted
High.
Description
S
R
ODDR
ug190_7_20_012207
Table 7-13
Description
Q
OPPOSITE_EDGE
(default), SAME_EDGE
0 (default), 1
ASYNC, SYNC (default)
lists the ODDR port
Possible Values
OLOGIC Resources
347
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