XC5VLX330-1FFG1760C Xilinx Inc, XC5VLX330-1FFG1760C Datasheet - Page 85
![IC FPGA VIRTEX-5 330K 1760FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX330-1FFG1760C
Manufacturer Part Number
XC5VLX330-1FFG1760C
Description
IC FPGA VIRTEX-5 330K 1760FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX330-1FFG1760C
Number Of Logic Elements/cells
331776
Number Of Labs/clbs
25920
Total Ram Bits
10616832
Number Of I /o
1200
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
For Use With
HW-V5-ML525-UNI-G - EVAL PLATFORM ROCKET IO VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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XC5VLX330-1FFG1760C
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Fixed-Phase Shifting
In
in phase with the desired clock phase. The clock outputs are phase-shifted to appear
sometime later than the input clock, and the LOCKED signal is asserted.
X-Ref Target - Figure 2-18
•
Figure
Clock Event 1
Clock event 1 appears after the desired phase shifts are applied to the DCM. In this
example, the shifts are positive shifts. CLK0 and CLK2X are no longer aligned to
CLKIN. However, CLK0, and CLK2X are aligned to each other, while CLK90 and
CLK180 remain as 90° and 180° versions of CLK0. The LOCK signal is also asserted
once the clock outputs are ready.
2-18, the DCM outputs the correct frequency. However, the clock outputs are not
LOCKED
CLK180
CLK2X
CLK90
CLKIN
CLK0
Figure 2-18: Phase Shift Example: Fixed
www.xilinx.com
Lock Time
1
ug190_2_19_042406
DCM Timing Models
85
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