XC5VSX240T-1FF1738CES Xilinx Inc, XC5VSX240T-1FF1738CES Datasheet - Page 40
XC5VSX240T-1FF1738CES
Manufacturer Part Number
XC5VSX240T-1FF1738CES
Description
IC FPGA V5 FX ES 240K 1738FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheet
1.XC5VLX30-1FFG324C.pdf
(91 pages)
Specifications of XC5VSX240T-1FF1738CES
Number Of Logic Elements/cells
239616
Number Of Labs/clbs
18720
Total Ram Bits
19021824
Number Of I /o
960
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
For Use With
HW-AFX-FF1738-500-G - BOARD DEV VIRTEX 5 FF1738
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Input/Output Logic Switching Characteristics
Table 60: ILOGIC Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Setup/Hold
T
T
T
T
Combinatorial
T
T
Sequential Delays
T
T
T
T
T
Set/Reset
T
ICE1CK
ISRCK
IDOCK
IDOCKD
IDI
IDID
IDLO
IDLOD
ICKQ
RQ
GSRQ
RPW
Symbol
/T
/T
/T
/T
ICKSR
IOCKD
ICKCE1
IOCKDD
CE1 pin Setup/Hold with respect to CLK
SR/REV pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK without Delay
DDLY pin Setup/Hold with respect to CLK (using IODELAY)
D pin to O pin propagation delay, no Delay
DDLY pin to O pin propagation delay (using IODELAY)
D pin to Q1 pin using flip-flop as a latch without Delay
DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY)
CLK to Q outputs
SR/REV pin to OQ/TQ out
Global Set/Reset to Q outputs
Minimum Pulse Width, SR/REV inputs
Description
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
–0.24
–0.20
–0.12
–0.09
0.43
0.24
0.20
0.44
0.47
1.12
7.30
0.78
0.85
0.34
0.31
0.41
-3
Speed Grade
–0.24
–0.20
–0.12
–0.09
0.49
1.00
0.37
0.33
0.26
0.22
0.50
0.46
0.52
1.28
7.30
0.95
-2
–0.24
–0.20
–0.12
–0.08
10.10
0.59
1.22
0.39
0.36
0.30
0.26
0.58
0.55
0.60
1.53
1.20
-1
ns, Min
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
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