AT40K40-2DQI Atmel, AT40K40-2DQI Datasheet - Page 34

• Manufacturer Part Number: AT40K40-2DQI
• Description: IC FPGA 40K GATES 208PQFP
• Manufacturer: Atmel
• Series: AT40K/KLVr

Specifications of AT40K40-2DQI

• Number Of Logic Elements/cells: 2304
• Total Ram Bits: 18432
• Number Of I /o: 161
• Number Of Gates: 50000
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Labs/clbs: -
• Other names: AT40K402DQI

AC Timing Characteristics – 3.3V Operation AT40KLV
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V
Minimum times based on best case: V
Maximum delays are the average of t
All input IO characteristics measured from a V
V
All input IO characteristics measured from a V
V
34
Cell Function
Repeaters
Repeater
Repeater
Repeater
Repeater
Repeater
Repeater
Cell Function
IO
Input
Input
Input
Input
Output, Slow
Output, Medium
Output, Fast
Output, Slow
Output, Slow
Output, Medium
Output, Medium
Output, Fast
Output, Fast
DD
DD
. All output IO characteristics are measured as the average of t
. All output IO characteristics are measured as the average of t
AT40K/AT40KLV Series FPGA
Parameter
t
t
t
t
t
t
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PZX
PXZ
PZX
PXZ
PZX
PXZ
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
PDLH
CC
CC
= 3.6V, temperature = 0°C
and t
= 3.0V, temperature = 70°C
IH
IH
PDHL
Path
L -> E
E -> E
L -> L
E -> L
E -> IO
L -> IO
Path
pad -> x/y
pad -> x/y
pad -> x/y
pad -> x/y
x/y/E/L -> pad
x/y/E/L -> pad
x/y/E/L -> pad
oe -> pad
oe -> pad
oe -> pad
oe -> pad
oe -> pad
oe -> pad
of 50% of V
of 50% of V
.
DD
DD
at the pad (CMOS threshold) to the internal V
at the pad (CMOS threshold) to the internal V
PDLH
PDLH
and t
and t
PDHL
PDHL
11.5
17.4
2.2
2.2
2.2
2.2
1.4
1.4
1.9
5.8
9.1
7.6
6.2
9.5
2.1
7.4
2.7
5.9
2.4
-3
-3
to the pad V
to the pad V
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IH
IH
of 50% of V
of 50% of V
Notes
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
Notes
No extra delay
1 extra delay
2 extra delays
3 extra delays
50 pf load
50 pf load
50 pf load
50 pf load
50 pf load
50 pf load
50 pf load
50 pf load
50 pf load
DD
DD
0896C–FPGA–04/02
.
.
IH
IH
of 50% of
of 50% of