AT40K40AL-1FQC Atmel, AT40K40AL-1FQC Datasheet - Page 8

• Manufacturer Part Number: AT40K40AL-1FQC
• Description: IC FPGA 40K GATES 304PQFP
• Manufacturer: Atmel
• Series: AT40KALr

Specifications of AT40K40AL-1FQC

• Number Of Logic Elements/cells: 2304
• Total Ram Bits: 18432
• Number Of I /o: 256
• Number Of Gates: 50000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 304-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Labs/clbs: -
• Other names: AT40K40AL1FQC

Cell Connections
The Cell
8
AT40KAL Series FPGA
Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors.
Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per
busing plane) and five vertical local buses (1 per busing plane).
Figure 4. Cell Connections
Figure 5 depicts the AT40KAL cell. Configuration bits for separate muxes and pass
gates are independent. All permutations of programmable muxes and pass gates are
legal. V
nected to the horizontal local bus in plane n. A local/local turn in plane n is achieved by
turning on the two pass gates connected to V
nals into the cell from a local bus or to drive a signal out onto a local bus. Signals coming
into the logic cell on one local bus plane can be switched onto another plane by opening
two of the pass gates. This allows bus signals to switch planes to achieve greater route
ability. Up to five simultaneous local/local turns are possible.
The AT40KAL FPGA core cell is a highly configurable logic block based around two 3-
input LUTs (8 x 1 ROM), which can be combined to produce one 4-input LUT. This
means that any core cell can implement two functions of 3 inputs or one function of 4
inputs. There is a Set/Reset D flip-flop in every cell, the output of which may be tri-stated
and fed back internally within the core cell. There is also a 2-to-1 multiplexer in every
cell, and an upstream AND gate in the “front end” of the cell. This AND gate is an impor-
tant feature in the implementation of efficient array multipliers.
With this functionality in each core cell, the core cell can be configured in several
“modes”. The core cell flexibility makes the AT40KAL architecture well suited to most
digital design application areas, see Figure 6.
CELL
CELL
CELL
n
(V
1
(a) Cell-to-cell Connections
- V
5
) is connected to the vertical local bus in plane n. H
CELL
CELL
CELL
Direct Connect
Orthogonal
Direct Connect
CELL
CELL
CELL
Diagonal
n
and H
Plane 5
Plane 4
Plane 3
Plane 2
Plane 1
n
. Pass gates are opened to let sig-
⎧
⎨
⎩
⎧
⎨
⎩
⎧
⎨
⎩
⎧
⎨
⎩
⎧
⎨
⎩
(b) Cell-to-bus Connections
Busing Plane
Vertical
W
X
Y
Z
L
WXYZL
CELL
n
(H
2818F–FPGA–07/06
1
- H
⎫
⎪
⎬
⎪
⎭
Horizontal
Busing Plane
5
) is con-