EP2S130F1508I5 Altera, EP2S130F1508I5 Datasheet - Page 159
EP2S130F1508I5
Manufacturer Part Number
EP2S130F1508I5
Description
IC STRATIX II FPGA 130K 1508FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S130F1508I5
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
1126
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1508-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S130F1508I5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2S130F1508I5N
Manufacturer:
ALTERA
Quantity:
329
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Altera Corporation
April 2011
4.
5.
The Quartus II software reports the timing with the conditions shown in
Table 5–34
circuit that is represented by the output timing of the Quartus II software.
Figure 5–4. Output Delay Timing Reporting Setup Modeled by Quartus II
Notes to
(1)
(2)
(3)
Figures 5–5
output enable timing.
Record the time to V
Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
V
V
CCPD
CCINT
Output
Buffer
Figure
V
GND
CCIO
is 3.085 V unless otherwise specified.
is 1.12 V unless otherwise specified.
using the above equation.
and
5–4:
Output
5–6
V
show the measurement setup for output disable and
MEAS
MEAS
R
.
S
GND
V
TT
R
C
Stratix II Device Handbook, Volume 1
Figure 5–4
T
L
DC & Switching Characteristics
shows the model of the
Output
Output
p
n
R
D
5–23
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