XC4005-5PQ160C Xilinx Inc, XC4005-5PQ160C Datasheet - Page 33
XC4005-5PQ160C
Manufacturer Part Number
XC4005-5PQ160C
Description
IC LOGIC CL ARRAY 5000GAT 160PQF
Manufacturer
Xilinx Inc
Series
XC4000r
Datasheet
1.XC4003-6PQ100C.pdf
(40 pages)
Specifications of XC4005-5PQ160C
Number Of Logic Elements/cells
466
Number Of Labs/clbs
196
Total Ram Bits
6272
Number Of I /o
112
Number Of Gates
5000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
160-BQFP
Case
QFP160
Dc
97+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1050
XC4005-5PQ160C-0300
XC4005-5PQ160C03
XC4005-5PQ160C-0300
XC4005-5PQ160C03
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4005-5PQ160C
Manufacturer:
XILINX
Quantity:
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Company:
Part Number:
XC4005-5PQ160C
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CCLK
INIT
Notes:
Synchronous Peripheral Mode Programming Switching Characteristics
CCLK
RDY/BUSY
Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in
the first data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on
every eighth consecutive rising edge of CCLK.
The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation
does not require such a response.
The pin name RDY/BUSY is a misnomer; in Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
Note that data starts to shift out serially on the DOUT pin 0.5 CLK periods after it was loaded in parallel. This obviously
requires additional CCLK pulses after the last byte has been loaded.
DOUT
INIT (High) Setup time required
D0-D7 Setup time required
D0-D7 Hold time required
CCLK High time
CCLK Low time
CCLK Frequency
Description
BYTE
0
0
1
2-39
1
2
3
Symbol
2
T
T
T
T
T
F
IC
DC
CD
CCH
CCL
CC
BYTE 0 OUT
3
4
Min
60
50
60
5
0
5
BYTE
1
6
Max
7
8
BYTE 1 OUT
0
Units
MHz
ns
ns
ns
ns
1
s
X6096