XC2018-70PC68C Xilinx Inc, XC2018-70PC68C Datasheet - Page 27

• Manufacturer Part Number: XC2018-70PC68C
• Description: IC LOGIC CL ARRAY 1800GAT 68PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC68C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 58
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1003

Figure 20. Typical Power Consumption by Element
Figure 21. LCA Power Distribution
Vcc
0.001
1000
GND
GND
0.01
100
0.01
1.0
0.1
100
10
1.0
0.1
10
0.1
0.1
XC2000L
XC2000
1
1
Vcc
Frequency (MHz)
Frequency (MHz)
Logic
Power Grid
Ground and
Vcc Ring for
I/O Drivers
X5422
10
10
2-211
independent matrix of V
interior logic of the device. This power distribution grid
provides a stable supply and ground for all internal logic,
providing the external package power pins are appropri-
ately decoupled. Typically a 0.1 F capacitor connected
between the V
provide adequate decoupling.
Output buffers capable of driving the specified 4 mA loads
under worst-case conditions may be capable of driving 25
to 30 times that current in a best case. Noise can be
reduced by minimizing external load capacitance and
reducing simultaneous output transitions in the same
direction. It may also be beneficial to locate heavily loaded
output buffers near the ground pads. Multiple V
ground pin connections are required for package types
which provide them.
100
100
One device output with a
50 pF load (0.7 mW/MHz)
One CLB driving three local
interconnects (0.05 mW/MHz)
One global clock buffer and
clock line (0.4 mW/MHz)
One device output with a
50 pF load (1.5 mW/MHz)
One global clock buffer and
clock line (1.0 mW/MHz)
One CLB driving three local
interconnects (0.15 mW/MHz)
CC
and ground pins near the package will
CC
X5305
and ground lines supplies the
X5304
CC
and