XC3020A-7PC68C Xilinx Inc, XC3020A-7PC68C Datasheet - Page 24

IC LOGIC CL ARRAY 2000GAT 68PLCC

XC3020A-7PC68C

Manufacturer Part Number
XC3020A-7PC68C
Description
IC LOGIC CL ARRAY 2000GAT 68PLCC
Manufacturer
Xilinx Inc
Series
XC3000A/Lr
Datasheet

Specifications of XC3020A-7PC68C

Number Of Labs/clbs
64
Total Ram Bits
14779
Number Of I /o
58
Number Of Gates
1500
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
68-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
Other names
122-1009

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC3020A-7PC68C
Manufacturer:
XILINX
Quantity:
3 253
Part Number:
XC3020A-7PC68C
Manufacturer:
XILINX
0
Part Number:
XC3020A-7PC68C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Company:
Part Number:
XC3020A-7PC68C
Quantity:
260
Part Number:
XC3020A-7PC68C/I
Manufacturer:
XILINX
0
XC3000 Series Field Programmable Gate Arrays
Notes: 1. At power-up, V
Figure 24: Master Serial Mode Programming Switching Characteristics
7-26
CCLK
Serial Data In
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
3. Master-serial-mode timing is based on slave-mode testing.
Serial DOUT
holding RESET Low until V
non-monotonically rising V
after VCC has reached 4.0 V (2.5 V for the XC3000L).
High.
(Output)
(Output)
CCLK
Data In setup
Data In hold
Description
CC
Product Obsolete or Under Obsolescence
n – 3
must rise from 2.0 V to V
1
CC
CC
T
DSCK
may require >6- s High level on RESET, followed by a >6- s Low level on RESET and D/P
n
has reached 4.0 V (2.5 V for the XC3000L). A very long V
1
2
T
C
DSCK
KDS
Symbol
CC
n – 2
min in less than 25 ms. If this is not possible, configuration can be delayed by
2 T
CKDS
n + 1
Min
n – 1
60
0
n + 2
CC
rise time of >100 ms, or a
November 9, 1998 (Version 3.1)
Max
n
Units
X3223
ns
ns
R

Related parts for XC3020A-7PC68C