XC4020E-3HQ240C Xilinx Inc, XC4020E-3HQ240C Datasheet - Page 61
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XC4020E-3HQ240C
Manufacturer Part Number
XC4020E-3HQ240C
Description
IC FPGA 784 CLB'S 240-HQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet
1.XC4005E-4PC84C.pdf
(68 pages)
Specifications of XC4020E-3HQ240C
Number Of Logic Elements/cells
1862
Number Of Labs/clbs
784
Total Ram Bits
25088
Number Of I /o
193
Number Of Gates
20000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-BFQFP Exposed Pad
Case
QFP240
Dc
99+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1117
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4020E-3HQ240C
Manufacturer:
XILINX
Quantity:
1 200
Figure 57: Synchronous Peripheral Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
CCLK
INIT
CCLK
2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
first data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
not require such a response.
additional CCLK pulses are clearly required after the last byte has been loaded.
RDY/BUSY
R
DOUT
INIT (High) setup time
D0 - D7 setup time
D0 - D7 hold time
CCLK High time
CCLK Low time
CCLK Frequency
Product Obsolete or Under Obsolescence
Description
BYTE
0
XC4000E and XC4000X Series Field Programmable Gate Arrays
0
1
Symbol
T
T
T
T
F
T
CCH
CCL
DC
CD
CC
IC
2
BYTE 0 OUT
3
4
Min
60
50
60
5
0
5
BYTE
1
6
Max
8
7
BYTE 1 OUT
0
Units
MHz
1
ns
ns
ns
ns
s
X6096
6-65
6