XC4005XL-09PC84C Xilinx Inc, XC4005XL-09PC84C Datasheet - Page 4
XC4005XL-09PC84C
Manufacturer Part Number
XC4005XL-09PC84C
Description
IC FPGA C-TEMP 3.3V 84-PLCC
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet
1.XC4005XL-09PC84C.pdf
(4 pages)
Specifications of XC4005XL-09PC84C
Number Of Logic Elements/cells
466
Number Of Labs/clbs
196
Total Ram Bits
6272
Number Of I /o
61
Number Of Gates
5000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
84-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
XC4000E Logic Cell Array Family
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
* Timing is based on the XC4005E. For other devices see XACT timing calculator.
Combinatorial Delays
CLB Fast Carry Logic
Sequential Delays
Set-up Time before Clock K
Hold Time after Clock K
Clock
Set/Reset Direct
Master Set/Reset*
Description
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
C inputs via H’ to X/Y outputs
Operand inputs (F1,F2,G1,G4) to C
Add/Subtract input (F3) to C
Initialization inputs (F1,F3) to C
C
C
Clock K to outputs Q
F/G inputs
F/G inputs via H’
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
C
C
F/G inputs
F/G inputs via H’
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
Clock High time
Clock Low time
Width (High)
Delay from C inputs via S/R, going High to Q
Width (High or Low)
Delay from Global Set/Reset net to Q
IN
IN
IN
IN
through function generators to X/Y outputs
to C
input via F'/G'
input via F'/G' and H'
OUT
, bypass function generators.
OUT
OUT
OUT
Speed Grade
4
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
ILO
IHO
HHO
OPCY
ASCY
INCY
SUM
BYP
CKO
ICK
IHCK
HHCK
DICK
ECCK
RCK
CCK
CHCK
CKI
CKIH
CKHH
CKDI
CKEC
CKR
CH
CL
RPW
RIO
MRW
MRQ
Min
-4
Max
Min Max
18.9
2.3
4.0
3.3
1.9
2.6
1.7
0
0
0
0
0
0
4.0
4.0
4.0
-3
14.4
2.0
3.6
2.9
2.6
4.4
1.7
3.3
0.7
2.4
4.0
Min Max Units
-2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns